Random number generating circuit, semiconductor integrated circuit, IC card and information terminal device

ABSTRACT

A random number generating circuit receives as input a first digital random number signal generated at a first generating rate and produces as output a second digital random number signal having a second generating rate that is twice as high as the first generating rate. A semiconductor integrated circuit, an IC card and an information terminal device comprising the random number circuit is provided.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2003-341983, filed on Sep. 30,2003; the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

The invention relates to a random number generating circuit,semiconductor integrated circuit, IC card and information terminaldevice. In particular, the invention relates to a random numbergenerating circuit, semiconductor integrated circuit, IC card andinformation terminal device capable of generating high-quality digitalrandom number signals at high rates.

In recent years, sophisticated physical random numbers have beenincreasingly needed in information security, simulation and other areas.In particular, from the viewpoint of ensuring security in mobile devicessuch as IC cards and cellular phones, a small-size random number circuitis required which can generate high-quality random numbers at highrates. However, in physical random number generators, there has oftenbeen a tradeoff between the rate of generating random numbers and theirquality. It has been a problem that the generating rate is forced to belowered to ensure a sufficient quality of random numbers with asmall-size physical random number circuit.

A solution to the problem is, for example, to provide a plurality ofrandom number circuits, each outputting 1-bit physical random numbers.The plurality of outputs are sequentially read out, thereby beingregarded as a 1-bit random number sequence. However, this solution hasproblems that it is difficult to provide a plurality of physical randomnumber circuits having similar characteristics, and that the circuitscale increases.

Another solution is to store data in a memory and rapidly read it outwhen needed. However, this solution has problems that the frequency ofusing random numbers is limited in order to ensure sufficient time forstoring the random number data. To avoid this problem, a stored randomnumber sequence is operated with a slowly generated random numbersequence to form a new random number sequence which is stored back inthe memory (Japanese Laid-Open Patent Application (Kokai) 2001-290634).While this solution overcomes the problem of the generating rate, it hasa problem that the random numbers exhibit periodicity because theinformation of the same random numbers is repeatedly used.

As described above, in the conventional art, it is not easy to generatehigh-quality random numbers at high rates with a small-scale circuit.

SUMMARY OF THE INVENTION

The invention provides a random number generating circuit in whichrandom numbers with a higher generating rate can be obtained from therandom number generating circuit which outputs 1-bit physical randomnumbers without using a plurality of random number circuits. A featureof the random number generating circuit is that a digital waveformrepresenting a certain physical random number sequence is transformedinto a digital waveform representing a faster, in particular, twofoldfaster random number sequence by utilizing the original random numbersequence. The generating rate can be further increased by repeating thetwofold speedup.

More specifically, according to an aspect of the invention, there isprovided a random number generating circuit that receives as input afirst digital random number signal having a first generating rate andproduces as output a second digital random number signal having a secondgenerating rate that is twice as high as the first generating rate.

According to another aspect of the invention, there is provided asemiconductor integrated circuit comprising a random number generatingcircuit that receives as input a first digital random number signalgenerated at a first generating rate and produces as output a seconddigital random number signal having a second generating rate that istwice as high as the first generating rate.

According to another aspect of the invention, there is provided an ICcard comprising a semiconductor integrated circuit having a randomnumber generating circuit that receives as input a first digital randomnumber signal generated at a first generating rate and produces asoutput a second digital random number signal having a second generatingrate that is twice as high as the first generating rate.

According to another aspect of the invention, there is provided aninformation terminal device comprising a semiconductor integratedcircuit having a random number generating circuit that receives as inputa first digital random number signal generated at a first generatingrate and produces as output a second digital random number signal havinga second generating rate that is twice as high as the first generatingrate.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood more fully from the detaileddescription given herebelow and from the accompanying drawings of theembodiments of the invention. However, the drawings are not intended toimply limitation of the invention to a specific embodiment, but are forexplanation and understanding only.

In the drawings:

FIG. 1 is a block diagram of a random number generating circuitaccording to an embodiment of the invention;

FIG. 2 is a schematic diagram showing a first specific example of therandom number generating circuit according to the invention;

FIG. 3 is a schematic diagram showing a specific example of the counter111 and combiner 112;

FIG. 4 is a schematic diagram showing a specific example of the edgedetector 121;

FIG. 5 is a schematic diagram showing a specific example of the shiftregister 131;

FIG. 6 is a schematic diagram showing a specific example of the combiner140;

FIG. 7 is a block diagram showing a specific example in which thehigh-rate signal introducing unit 120 and the smoothing unit 130 areintegrated together;

FIG. 8 is a block diagram showing a random number generating circuitcomprising a continuous signal processing unit 110 using a pulsegenerator 113;

FIG. 9 is a schematic diagram showing a specific example of the pulsegenerator 113;

FIG. 10 is a schematic diagram showing a configuration in which acounter value used in the continuous signal processing unit 110 isreused;

FIG. 11 is a schematic diagram showing a specific example of the counter111, shift register 131, decoder 135 and selector 134 in the circuitconfiguration shown in FIG. 10;

FIG. 12 is a block diagram showing a random number generating circuit inwhich a scrambling circuit is used in the smoothing unit 130;

FIG. 13 is a schematic diagram showing a specific example of thescrambling circuit 133;

FIG. 14 is a schematic diagram showing another specific example of thescrambling circuit 133;

FIG. 15 is a block diagram showing a configuration in which the randomnumber generating circuits according to the invention are connected inseries, with their rates being successively twofold higher;

FIG. 16 is a schematic diagram showing the variation of waveforms whenthe circuit configuration shown in FIG. 2 is used to repeatedlytransform the digital waveforms as shown in FIG. 15;

FIG. 17 is a schematic diagram showing a configuration of a relevantpart of the semiconductor integrated circuit according to the specificexample of the invention;

FIG. 18 is a conceptual diagram for illustrating the circuit scale ofthe semiconductor integrated circuit 200 according to the specificexample of the invention;

FIG. 19 is a schematic diagram showing an IC card and informationterminal device according to the specific example of the invention; and

FIG. 20 is a schematic diagram showing a cellular phone as a specificexample of the invention.

DETAILED DESCRIPTION

Embodiments of the invention will now be described in detail withreference to the drawings.

FIG. 1 is a block diagram of a random number generating circuitaccording to an embodiment of the invention.

More specifically, the random number generating circuit 100 according tothe invention comprises a continuous signal processing unit 110, ahigh-rate signal introducing unit 120 and a smoothing unit 130. Therandom number generating circuit 100 serves to transform random numberdata generated by the physical random number generating unit 50. Thephysical random number generating unit 50 may or may not be included aspart of the random number generating circuit 100.

A feature of the random number generating circuit 100 according thepresent embodiment is that a digital waveform representing a certainrandom number sequence is transformed into a digital waveform having atwofold higher generating rate. More specifically, as illustrated in thefigure, a digital random number signal of A bits per second (bits/s)generated by the physical random number generating unit 50 istransformed into a random number signal of 2A bits per second by therandom number generating circuit 100. Furthermore, according to theinvention, the signal sequence remains to be a random number sequenceeven if the generating rate of the random number signal is doubled, thatis, the rate of reading out the digital value is doubled. In otherwords, when the High and Low levels of the digital signal are depictedwith respect to time, the operation performed by the random numbergenerating circuit 100 according to the present embodiment is viewed asgenerating a digital signal in which one piece of signal varies in halfduration as compared to the signal before transformation.

To achieve such transformation of digital random numbers, the randomnumber generating circuit 100 according to the invention comprises acontinuous signal processing unit 110, a high-rate signal introducingunit 120 and a smoothing unit 130.

The continuous signal processing unit 110 serves to divide a long run of“0” or “1” signals. This can avoid disruption of the balance between“0s” and “1s” as random numbers when the frequency of the long run ofsignals is doubled. For example, when the quality of random numbers isdesired to pass the test of FIPS 140-2 (Federal Information ProcessingStandards Publication: FIPS PUB 140-2 (2001)), even a run of 20identical digits passes the test, but its double, i.e., a run of 40digits fails the test. The continuous signal processing unit 110 isprovided to avoid this situation. While the above-mentioned specificexample is based on FIPS 140-2, the acceptable run length can beappropriately determined according to practical use conditions.

The high-rate signal introducing unit 120 serves to introduce a signalcomponent having one half of a clock width. In other words, thegenerating rate of the digital random number signals can be doubled byintroducing a component with a signal width being one half in thehigh-rate signal introducing unit 120.

The smoothing unit 130 serves to perform smoothing by adjusting thebalance between “0s” and “1s” as a random number sequence. Morespecifically, the smoothing unit 130 corrects the “deviation” of balancebetween “0s” and “1s” due to the deformation by the continuous signalprocessing unit 110 and the high-rate signal introducing unit 120,thereby serving to adjust the balance between “0s” and “1s” as a randomnumber sequence. In the sense of adjusting balance, the smoothing unit130 plays a role close to that of the continuous signal processing unit110.

The deformation of digital signals by the continuous signal processingunit 110, high-rate signal introducing unit 120 and smoothing unit 130maybe performed separately. Alternatively, some or all of thedeformations may be performed simultaneously, or in a different order.

Next, a specific example of the configuration of the random numbergenerating circuit for achieving speedup according to the presentembodiment will be described.

FIG. 2 is a schematic diagram showing a first specific example of therandom number generating circuit according to the invention. In thefigure, the elements similar to those described with reference to FIG. 1are labeled with like reference numerals and will not be described indetail. First, a clock having a frequency of A hertz (Hz) is inputted tothe random number generator 50, which produces a digital random numbersignal of A bits per second. This random number signal is first inputtedto the continuous signal processing unit 110.

The continuous signal processing unit 110 comprises a counter 111 and acombiner 112. The counter 111 is used to count how many times the samedigit continues to repeat in the inputted digital random number signal.When the number of continued repetitions is more than or equal to acertain threshold, the combiner 112 combines the original random numberwith its inverse value. The digital random number signal to which thecontinuous signal processing has been applied is inputted separately tothe high-rate signal introducing unit 120 and the smoothing unit 130.

FIG. 3 is a schematic diagram showing a specific example of the counter111 and combiner 112.

More specifically, the counter 111 comprises an ON state counting unit11A and an OFF state counting unit 111B. The ON state counting unit 111Aand the OFF state counting unit 111B are connected such that the clockenable terminal CE is High when the random number output is ON and OFF,respectively. When the clock enable terminal CE is High, each counter CTstarts counting. The circuit that precedes the counter CT and comprisesa D-flip-flop, inverter(s) and AND gate is a falling edge detector,which outputs a signal for one clock to reset the counter when therandom number output changes from ON to OFF and from OFF to ON,respectively. This example is configured such that a signal is outputtedwhen the same value continues for eight clocks in the random numberoutput. The combiner 112 achieves combining by making an exclusive-ORamong the outputs of the respective counters 111A, 111B and the originalrandom number.

It should be noted that the signal processing in the continuous signalprocessing unit 110 is not limited to those achieved by the counter 111.For example, as described later in detail, a method may be used whichsynthesizes a pulse signal that produces a High level at a fixedinterval.

Returning to FIG. 2, the high-rate signal introducing unit 120 comprisesan edge detecting unit 121 and a combiner 140. The edge detecting unit121 detects a rising and falling edge of the inputted signal by using aclock CL2 having a frequency of twice as high as the frequency A of aclock CL1 that has generated the original random number. Introducinghigh-rate components is based on the detected edges.

FIG. 4 is a schematic diagram showing a specific example of the edgedetector 121. More specifically, the edge detector 121 may comprise, forexample, a flip-flop and an exclusive-OR circuit.

On the other hand, the smoothing unit 130 shown in FIG. 2 comprises ashift register 131, and shares the combiner 140 with the high-ratesignal introducing unit 120.

FIG. 5 is a schematic diagram showing a specific example of the shiftregister 131. More specifically, the shift register 131 can beconfigured by aligning a plurality of flip-flops FD. The shift register131 can be used to shift its waveform by several clocks for smoothing.The simplest way to perform smoothing is to make an exclusive-OR withanother random number sequence. In a 1-bit random number source, onecannot obtain another random number sequence by nature. However, it canbe used for smoothing by utilizing the property that the random numbershave no autocorrelation and effectively regarding the shifted version ofthe random number sequence as another random number sequence. An edgesignal outputted from the edge detecting unit 121 and the signal shiftedin the shift register 131 are inputted to the combiner 140, and anexclusive-OR between them is obtained. As a result, a digital randomnumber signal can be obtained which is outputted at a bit rate twice ashigh as that of the original random number sequence.

FIG. 6 is a schematic diagram showing a specific example of the combiner140. More specifically, the outputs from the shift register 131 (orscrambling circuit or other circuits described later) and from the edgedetector 121 can be combined by using an exclusive-OR circuit.

In this specific example again, the continuous signal processing unit110, high-rate signal introducing unit 120 and smoothing unit 130 can bearranged in a different order as described above with reference to FIG.1.

FIG. 7 is a block diagram showing a specific example in which thehigh-rate signal introducing unit 120 and the smoothing unit 130 areintegrated together. More specifically, if the random numbers have noautocorrelation, a random number sequence and its shifted version can beviewed as effectively different random number sequences. As a result,provided that an exclusive-OR is finally taken in the combiner 140,introducing a component having a frequency of 2 A hertz (Hz) into thesignal before shifting is equivalent to introducing the component havinga frequency of 2 A hertz (Hz) into the shifted signal. For the samereason, smoothing may be performed first in the smoothing unit 130, andthen the processing may be continued by the continuous signal processingunit 110 and the high-rate signal introducing unit 120.

Furthermore, also in this specific example, the signal processing in thecontinuous signal processing unit 110 is not limited to those achievedby the counter 111. A method may be used which synthesizes a pulsesignal that produces a High level at a fixed interval.

FIG. 8 is a block diagram showing a random number generating circuitcomprising a continuous signal processing unit 110 using a pulsegenerator 113. More specifically, a continuous digital random numbersignal can be divided by using a signal having an appropriate pulseinterval outputted from the pulse generator 113. In this method, whenthe high-rate random number generating circuit 100 according to theinvention is repeatedly used to introduce a periodic signal, the qualityof the random number sequence may be degraded, while there is anadvantage that the circuit scale can be reduced as compared to thatusing the counter 111. One can make meaningful use of the configurationof this specific example by determining an acceptable degree ofdegradation according to practical use conditions.

FIG. 9 is a schematic diagram showing a specific example of the pulsegenerator 113. More specifically, the pulse generator 113 can beconfigured by appropriately combining, for example, flip-flops FD,inverters and other logic circuits.

On the other hand, the smoothing unit 130 is not also necessarilylimited to the configuration using the shift register 131. For example,it may use such transformations as those performed at the beginning ofthe DES (data encryption standard) encryption algorithm in which a setof continuous signals are combined and rearranged.

Furthermore, when the smoothing is performed using the output of theshift register 131, the output can be randomly selected to enhance thequality of high-rate random numbers.

FIG. 10 is a schematic diagram showing a configuration in which acounter value used in the continuous signal processing unit 110 isreused. The counter 111 counts the length of ON states (or OFF states)for the random numbers outputted from the random number generator 50,and thus produces a random output. The value of the output can bedecoded with the decoder 135 and the number of shifts in the shiftregister 131 can be selected by the selector 134. Accordingly, thenumber of shifts for the shift register used in the smoothing can be setrandomly.

FIG. 11 is a schematic diagram showing a specific example of the counter111, shift register 131, decoder 135 and selector 134 in this circuitconfiguration.

FIG. 12 is a block diagram showing a random number generating circuit inwhich a scrambling circuit is used in the smoothing unit 130. Morespecifically, in this specific example, the scrambling circuit 133 isused to determine the number of clocks for the shift register 131. Thescrambling circuit 133 may utilize, for example, an oscillating circuit(not shown).

FIG. 13 is a schematic diagram showing a specific example of thescrambling circuit 133. More specifically, the scrambling circuitaccording to this specific example is an oscillating circuit ofdiscontinuous oscillation type. For two inputs X1 and X2, it yields twooutputs Q1 and Q2. When the two inputs X1 and X2 are equal, itsoperation is equivalent to that of a flip-flop comprising an even numberof inverters. On the other hand, when the two inputs X1 and X2 aredifferent, it is a ring oscillating circuit. Accordingly, when the twoinputs X1 and X2 are equal or different half-and-half, it oscillates forhalf a duration of the circuit operating period.

Furthermore, the circuit shown in FIG. 13 produces an output that alsodepends on the initial value Z, as opposed to a simple oscillatingcircuit. More specifically, given the initial value Z of “1”, when theinputs X1 and X2 are both “1”, the outputs Q1 and Q2 are both “0”. Whenthe inputs X1 and X2 are both “0”, the output Q1 is “1” and Q2 is “0”.

On the other hand, given the initial value Z of “0”, when the inputs X1and X2 are both “1”, the outputs Q1 and Q2 are both “1”. When the inputsX1 and X2 are both “0”, the output Q1 is “0” and Q2 is “1”.

As described above, the scrambling circuit 133 in the specific exampleof FIG. 13 can be referred to as “intermittent oscillating circuit” inthe sense that it oscillates only when its two inputs X1 and X2 aredifferent. The continuous oscillating circuit has shortcomings in thatits random number data tends to have persistent periodicity and that itconsumes large electric current. The intermittent oscillating circuit isa circuit that improves these points.

FIG. 14 is a schematic diagram showing another specific example of thescrambling circuit 133. More specifically, the scrambling circuitaccording to this specific example is a ring oscillator comprising threeinverters connected in series, and can be referred to as “continuousoscillating circuit”. In this case, it is desirable that the oscillatingfrequency is generally at least ten times as high as the system clock.

Accordingly, a number of these scrambling circuits 133 can be used toprovide inputs to the selector 134 as shown in FIG. 12. One or morevalues of the shift register 131 can thus be selected and XORed tofacilitate the smoothing. The random number generating circuit using thescrambling circuit 133 as described with reference to FIGS. 12 to 14 mayhave a larger circuit scale than that using the shift register 131.However, the former has less degradation due to repeated speedups and issuitable to enhancing the rate while preserving its high quality.

Alternatively, if the emerging probabilities of “0” and “1” are balancedwell in the output of the scrambling circuit 133, the output from thescrambling circuit 133 may be used for the smoothing as it is withoutusing the shift register 131.

On the other hand, the pseudo-random output may be utilized for thesmoothing. In this case, however, a problem that a periodicity of thepseudo-random number may be introduced into the random number sequencemay arise, while the smoothing can be easily performed. Any one of thesemethods may be appropriately selected by considering the conditionoperated or specification required.

FIG. 15 is a block diagram showing a configuration in which the randomnumber generating circuits according to the invention are connected inseries, with their rates being successively twofold higher. According tothe invention, the transformation in the random number generatingcircuit 100 can thus be repeated to accelerate the generating rate ofthe digital random number signal twofold for each iteration. As aresult, even a digital random number signal with very high rates can begenerated depending on applications.

FIG. 16 is a schematic diagram showing the variation of waveforms whenthe circuit configuration shown in FIG. 2 is used to repeatedlytransform the digital waveforms as shown in FIG. 15. As shown in thefigure, repeated twofold speedups gradually reduces the interval offluctuation of digital waveforms, which ensures randomness even when thesignal is rapidly read out.

Table 1 shows a FIPS 140-2 test result for the physical random numbersequence outputted at a rate of 9 kbits/s from the physical randomnumber generator 50.

TABLE 1 (9 kbits/s) [row 0] [row 1] [row 2] [row 3] [row 4] [row 5] [row6] [row 7] monobit 10101 10126 10082 9933 10033 9948 9980 9934 Poker17.9968 17.9392 24.6592 13.3696 17.0752 16.6976 14.7712 13.5552 test Runtest ‘0’ run 2575 2536 2393 2465 2487 2496 2459 2479 count[1] ‘0’ run1281 1245 1300 1226 1271 1288 1246 1254 count[2] ‘0’ run 609 582 628 606646 579 645 657 count[3] ‘0’ run 302 301 322 345 310 308 320 317count[4] ‘0’ run 135 143 137 165 137 163 157 169 count[5] ‘0’ run 152168 153 158 156 173 152 139 count[6] ‘1’ run 2509 2428 2422 2467 24922526 2481 2501 count[1] ‘1’ run 1285 1240 1191 1241 1237 1213 1242 1300count[2] ‘1’ run 650 652 670 619 646 657 626 615 count[3] ‘1’ run 318338 305 331 336 307 316 317 count[4] ‘1’ run 134 163 168 166 150 156 151145 count[5] ‘1’ run 158 154 177 141 147 148 163 138 count[6] Long runtest longest 11 14 12 13 10 13 15 13 run of ‘0’ longest 13 13 12 12 1211 13 14 run of ‘1’

Table 2 shows a FIPS 140-2 test result where this physical random numbersequence is accelerated up to 1.152 Mbits/s through seven iterations ofthe transformation by the random number generating circuit shown in FIG.2.

TABLE 2 (1.152 Mbits/s) [row 0] [row 1] [row 2] [row 3] [row 4] [row 5][row 6] [row 7] monobit 10025 9942 9944 10134 10044 9915 9958 10052Poker 29.9648 34.0736 11.5264 27.8528 6.6688 16.2496 40.4672 10.688 testRun test ‘0’ run 2566 2531 2460 2619 2501 2522 2606 2541 count[1] ‘0’run 1360 1350 1263 1287 1321 1249 1368 1201 count[2] ‘0’ run 640 622 618641 589 670 598 637 count[3] ‘0’ run 342 361 310 300 329 314 296 323count[4] ‘0’ run 150 137 180 154 148 185 158 146 count[5] ‘0’ run 97 125156 115 145 130 141 156 count[6] ‘1’ run 2591 2607 2529 2506 2531 25462573 2471 count[1] ‘1’ run 1323 1282 1246 1327 1218 1287 1343 1302count[2] ‘1’ run 645 659 622 668 644 657 716 616 count[3] ‘1’ run 337299 284 336 320 307 308 293 count[4] ‘1’ run 141 161 136 145 172 142 123163 count[5] ‘1’ run 119 118 170 135 148 130 104 160 count[6] Long runtest longest 10 10 13 12 11 12 11 11 run of ‘0’ longest 10 11 12 11 1011 10 15 run of ‘1’

It can be seen in Table 1 that at 9 kbits/s, the sequence has passed allthe tests without any problems. When it is accelerated up to 1.152Mbits/s, it has generally reached a level of passing the test.Consequently, according to the criterion of the FIPS 140-2 test,acceleration by at least two orders of magnitude is available.

As described above, the present circuit can be used to enhance thegenerating rate of random numbers by several orders of magnitude on acertain criterion which is established with respect to the quality ofthe random numbers. As a result, a digital random number signal of apredetermined quality can be generated at higher rates than before.

Next, a semiconductor integrated circuit (IC) comprising the randomnumber generating circuit according to the invention will be described.

FIG. 17 is a schematic diagram showing a configuration of a relevantpart of the semiconductor integrated circuit according to this specificexample. This specific example is an IC that can be mounted on an ICcard, for example. The IC comprises an operating unit (MPU), memory(RAM, ROM, EEPROM), auxiliary operating unit (co-processor), and randomnumber generating circuit 100. Here, the auxiliary operating unit(co-processor) serves to perform cryptographic processing.

The random number generating circuit 100 also includes the random numbergenerator 50 as illustrated in FIGS. 1 to 16. The random numbergenerating circuit 100 can generate a high-quality digital random numbersignal at high rates by combining the continuous signal processing unit110, high-rate signal introducing unit 120 and smoothing unit 130 asdescribed above. With the random number generating circuit 100 on board,the operating unit (MPU) and the auxiliary operating unit (co-processor)dedicated to cryptographic processing can always read out and usehigh-quality random numbers at high rates. The random numbers can alsobe used for disturbing the variation of electric current consumption asa countermeasure against hacking techniques for reading out theencryption key from the signal of electric current consumption of theIC. This can achieve a high level of cryptographic security.

FIG. 18 is a conceptual diagram for illustrating the circuit scale ofthe semiconductor integrated circuit 200 according to this specificexample. More specifically, the random number generating circuit 100according to the invention can be entirely configured from CMOS logiccircuits alone. Furthermore, it can be mounted on various ICs becausethe number of logic gates required is as low as several hundreds. Thecircuit scale is on the order of or smaller than that illustrated inFIG. 18, and free from any problems of significantly increasing theentire size of the IC.

With the random number generating circuit according to the invention onboard, sophisticated cryptographic security capabilities are madeavailable. It can also be used for random numbers in gaming machines andMonte Carlo simulations.

Next, an IC card and portable information terminal device on which therandom number generating circuit according to the invention is mountedwill be described.

FIG. 19 is a schematic diagram showing an IC card and informationterminal device according to this specific example. More specifically,in the figure, reference numeral 300 designates an IC card orinformation terminal device according to this specific example. The ICcard may include, for example, a bank deposit card or various otherprepaid cards, a company employee ID card and an access security card.The information terminal device may include, for example, a cellularphone or other portable terminals. The portable terminal may be providedwith one or more capabilities including, for example, word processor,spreadsheet, scheduler, game, transmitting and receiving emails, andtaking still or moving pictures.

For example, a cellular phone 300 as shown in FIG. 20 can be equippedwith the random number generating circuit 100 according to theinvention. It is also the case for similar portable informationterminals.

Furthermore, according to the invention, a high-quality digital randomnumber signal can be generated at high rates by combining the continuoussignal processing unit 110, high-rate signal introducing unit 120 andsmoothing unit 130 as described above. As a result, a high level ofcryptographic security capability can be added while greatly reducingthe size and suppressing power consumption. In other words, the randomnumber generating circuit 100 can be used, for example, for userauthentication process, encryption and decryption of treated data, aswell as game features and random numbers for Monte Carlo simulations.

As described above, the invention can achieve a random number generatingcircuit capable of generating highly genuine random numbers at highrates with a compact size, low power consumption and low cost. As aresult, it can be applied to, for example, an IC card or informationterminal device, to achieve a secure and inexpensive system, thuscontributing much to industrial fields.

Embodiments of the invention have been described with reference tospecific examples. However, the invention is not limited to the specificexamples described above.

For example, the specific configuration of the random number generator,continuous signal processing unit, high-rate signal introducing unit andsmoothing unit used in the invention is not limited to theabove-described specific examples. Instead, any variation that includescircuit replacements having similar operations or functions is to beencompassed within the scope of the invention.

For example, a logic circuit comprising a plurality of flip-flops havingan indeterminate output connected in parallel or in series can also beused for the random number generator.

The flip-flop used in the invention is not limited to the D-typeflip-flop illustrated in the specific example. Instead, various othertypes of flip-flops can be used.

While digital random numbers generated by the random number generatingcircuit according to the invention may be used directly, they may alsobe used as a seed for another arithmetic random number generatingcircuit to generate new random numbers.

1. A random number generating circuit, comprising: an input thatreceives a first digital random number signal generated at a firstgenerating rate; a continuous signal processing unit to process thefirst digital random number signal so that any of its high and lowlevels do not repeat more than or equal to a predetermined number oftimes; a high-rate signal introducing unit to introduce a signalcomponent corresponding to a second generating rate that is twice ashigh as the first generating rate into the first digital random numbersignal; a smoothing unit to control a frequency of occurrence for thehigh and low levels in a data sequence of the second digital randomnumber signal; and an output to thereby output a second digital randomnumber having the second generating rate.
 2. The random numbergenerating circuit according to claim 1, wherein the continuous signalprocessing unit includes: a counter to count the number of continuedrepetitions of any of the high and low levels; and a first combiningunit to output a level different from the repeated level when the numberof continued repetitions measured by the counter exceeds a predeterminedvalue.
 3. The random number generating circuit according to claim 2,wherein the smoothing unit includes: a shift register to shift the firstdigital random number signal; a decoder to decode an output of thecounter; a selector to select the number of shifts in the shift registerbased on an output of the decoder; and a second combining unit tocombine the first digital random number signal shifted by the shiftregister and the first digital random number signal not shifted by theshift register.
 4. The random number generating circuit according toclaim 1, wherein the continuous signal processing unit includes: a pulsegenerating unit to output a pulse signal at a fixed interval; and afirst combining unit to combine the first digital random number signalinputted and the pulse signal for output.
 5. The random numbergenerating circuit according to claim 1, wherein the high-rate signalintroducing unit introduces the signal component corresponding to thesecond generating rate by detecting a rising and falling edge of thelevels in the first digital random number signal generated at the firstgenerating rate.
 6. The random number generating circuit according toclaim 1, wherein the smoothing unit includes: a shift register to shiftthe first digital random number signal; and a second combining unit tocombine the first digital random number signal shifted by the shiftregister and the first digital random number signal not shifted by theshift register.
 7. The random number generating circuit according toclaim 1, wherein the second combining unit outputs an exclusive-ORbetween the first digital random number signal shifted by the shiftregister and the first digital random number signal not shifted by theshift register.
 8. A semiconductor integrated circuit, comprising: arandom number generating circuit that receives as an input a firstdigital random number signal generated at a first generating rate,wherein the random number generating circuit includes: a continuoussignal processing unit to process the first digital random number signalso that any of its high and low levels do not repeat more than or equalto a predetermined number of times; a high-rate signal introducing unitto introduce a signal component corresponding to a second generatingrate that is twice as high as the first generating rate into the firstdigital random number signal; a smoothing unit to control a frequency ofoccurrence for the high and low levels in a data sequence of the seconddigital random number signal; and an output to thereby output a seconddigital random number having the second generating rate.
 9. Thesemiconductor integrated circuit according to claim 8, wherein thecontinuous signal processing unit includes: a counter to count thenumber of continued repetitions of any of the high and low levels; and afirst combining unit to output a level different from the repeated levelwhen the number of continued repetitions measured by the counter exceedsa predetermined value.
 10. The semiconductor integrated circuitaccording to claim 8, wherein the high-rate signal introducing unitintroduces the signal component corresponding to the second generatingrate by detecting a rising and falling edge of the levels in the firstdigital random number signal generated at the first generating rate. 11.An IC card, comprising: a semiconductor integrated circuit including arandom number generating circuit that receives as an input a firstdigital random number signal generated at a first generating rate,wherein the random number generating circuit includes: a continuoussignal processing unit to process the first digital random number signalso that any of its high and low levels do not repeat more than or equalto a predetermined number of times; a high-rate signal introducing unitto introduce a signal component corresponding to a second generatingrate that is twice as high as the first generating rate into the firstdigital random number signal; a smoothing unit to control a frequency ofoccurrence for the high and low levels in a data sequence of the seconddigital random number signal; and an output to thereby output a seconddigital random number having the second generating rate.
 12. The IC cardaccording to claim 11, wherein the continuous signal processing unitincludes: a counter to count the number of continued repetitions of anyof the high and low levels; and a first combining unit to output a leveldifferent from the repeated level when the number of continuedrepetitions measured by the counter exceeds a predetermined value. 13.The IC card according to claim 11, wherein the high-rate signalintroducing unit introduces the signal component corresponding to thesecond generating rate by detecting a rising and falling edge of thelevels in the first digital random number signal generated at the firstgenerating rate.
 14. An information terminal device, comprising: asemiconductor integrated circuit including a random number generatingcircuit that receives as an input a first digital random number signalgenerated at a first generating rate, wherein the random numbergenerating circuit includes: a continuous signal processing unit toprocess the first digital random number signal so that any of its highand low levels do not repeat more than or equal to a predeterminednumber of times; a high-rate signal introducing unit to introduce asignal component corresponding to a second generating rate that is twiceas high as the first generating rate into the first digital randomnumber signal; a smoothing unit to control a frequency of occurrence forthe high and low levels in a data sequence of the second digital randomnumber signal; and an output to thereby output a second digital randomnumber having the second generating rate.
 15. The information terminaldevice according to claim 14, wherein the continuous signal processingunit includes: a counter to count the number of continued repetitions ofany of the high and low levels; and a first combining unit to output alevel different from the repeated level when the number of continuedrepetitions measured by the counter exceeds a predetermined value. 16.The information terminal device according to claim 14, wherein thehigh-rate signal introducing unit introduces the signal componentcorresponding to the second generating rate by detecting a rising andfalling edge of the levels in the first digital random number signalgenerated at the first generating rate.